In the present ultra large scale integrated circuits, packaging density is increasing, and a variety of fine processing techniques are being studied and developed. Design rule has already been of the order of sub-half-micron. One of the techniques developed to meet the requirement for such a strict miniaturization is the CMP (chemical mechanical polishing) technique. In the production process of semiconductor devices, this technique can completely planarize a layer to be exposed to light, thereby lightening the burden of exposure techniques and stabilizing the yield. This, therefore, is a technique essential for planarizing an interlayer insulation film or a BPSG film, shallow trench isolation, etc.
According to the conventional polishing method employed in the production process of semiconductor devices to planarize an inorganic insulation film, such as a silicon oxide insulation film formed by plasma-CVD (Chemical Vapor Deposition), low-pressure-CVD, etc., a substrate on which a film to be polished is formed is pressed against a polishing pad, and the substrate or the polishing pad is moved while feeding an abrasive between the film to be polished and the polishing pad.
A polishing pad made of polyurethane foam has commonly been used in the above-described method, which however is insufficient in the speed of polishing the inorganic insulation film, and involves the great problem that polishing flaws occur during polishing on the surface of the oxide film due to polishing particles. In the case of a pad made of a foamed or non-foamed resin, decreasing the hardness of the pad surface reduces the polishing flaws effectively, but materials of low hardness do not suit to planarize irregularities efficiently in the production of semiconductor devices. To solve the problem, pad materials compromising the reduction of polishing flaws and the improvement of flatness are used, but are not enough to solve the problem of polishing flaws.